Utilizing Coupled Process And Device Simulation
For Optimization Of Sub-quarter-micron CMOS
Technology
Author(s)
J. Wittl, A. Burenkov, K. Tietzel, A. Muller, J.
Lorenz & H. Ryssel
Abstract
Coupled process and device simulation was applied for the optimization of
sub-quarter-micron CMOS technology. Optimum conditions for critical ion
implantation steps were found. Especially it was shown that an increased
implantation dose of the source and drain extensions improves the device
performance. On this basis, the device performance achievable when shrink-
ing to the 0.15/27B generation of CMOS technology was estimated. Finally,
an example of the coupled three-dimensional process and device simulation
which indicates the role of 3D effects in small size CMOS transistors is
presented.
1 Int
Keywords
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