Computer And Experimental Study Of The
Gate Dielectric In A Memory Transistor
Author(s)
R. Avichail-Bibi, D. Fuks, A. Kiv & Ya. Roizin
Abstract
We demonstrate a novel approach that enables combining microscopic studies of
the behaviour of the injected charge (IC) in the gate dielectric (GD) of the
memory transistor and the description of kinetics of memory device service
parameters. To study the microscopic processes of the redistribution of the IC in
the GD a special package of programs was developed that allows the modelling
the migration of injected electrons and holes in the GD. The model accounts real
properties of dielectric (spatial distribution of local centres and their
characteristics, the dielectric constant and its changes on the microscopic
distances, a complex composition of dielectric, temperature conditions and the
geometry of the GD). The results of the computer simulation of microscopic
characteristics of the IC were used as input data for the commercial Device
simulation program "Medici". We found a correlation between microscopic
characteristics of IC in GD and the service parameters of the memory device and
realized the feedback procedure changing the GD characteristics in the
simulation model.
Keywords: memory transistor, gate dielectric, trapping mechanisms, molecular
dynamics, computer simulation.
1 Introduction
The NROM (nitride read only memories) are non-volatile memories with local
storage of charge at the edges of the memory transistor channel and a thick
(>35 Å) bottom oxide (BOX) [1] that became popular in the nonvolatile
semiconductor memory market. A ONO (SiO2-Si3N4-SiO2) stack with nontunnel
bottom oxide is the GD in a two-bit per cell memory transistor.
Keywords
memory transistor, gate dielectric, trapping mechanisms, molecular
dynamics, computer simulation.
Related Book
Other papers in this volume
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